In general, MOS transistors in semiconductor devices have a structure where conductivity between a source corresponding to a negative electrode and a drain corresponding to a positive electrode is controlled by a voltage applied to a gate as a third electrode.
The gate comprises a gate oxide film and a polysilicon gate provided in a device region of a semiconductor substrate. A spacer formed of an insulation film is provided at side walls of the polysilicon gate.
In addition, the source and drain are provided in a junction region of the semiconductor substrate contacting an LDD (lightly doped drain). The source and drain have impurities of the same conductivity as the LDD injected therein at high concentration
On the other hand, semiconductor devices whose reliability and performance have been improved by including a dual gate have been recently developed. A variety of techniques for forming the dual gate are described in U.S. Pat. No. 5,024,960, U.S. Pat. No. 5,670,397, U.S. Pat. No. 5,770,490 and U.S. Pat. No. 6,214,671.